// The single-cycle operations: add, sub, and, xor. Registers A op B on the edge.
//
// Subtraction is the only one that can overflow: with 8-bit operands and a
// 16-bit result, neither the addition nor the multiplication can. A - B with
// A < B can, and that is why ovf_1c exists. The result in that case is the
// two's complement truncated to 16 bits -- it wraps to 0xFFxx -- which is what
// the hardware does and what the scoreboard has to predict correctly.
module vtalu_1c (
    input  logic [ 7:0] A,
    input  logic [ 7:0] B,
    input  logic        clk,
    input  logic [ 2:0] op,
    input  logic        reset_n,
    input  logic        start,
    output logic        done_1c,
    output logic        ovf_1c,
    output logic [15:0] result_1c
);

   // The two resets are deliberately different: the one on the result is
   // SYNCHRONOUS and the one on done is ASYNCHRONOUS. Not an oversight: the spec.
   always_ff @(posedge clk) begin
      if (!reset_n) begin
         result_1c <= 16'h0000;
         ovf_1c    <= 1'b0;
      end else if (start) begin
         ovf_1c <= (op == 3'b010) && (A < B);
         case (op)
            3'b001:  result_1c <= {8'h00, A} + {8'h00, B};
            3'b010:  result_1c <= {8'h00, A} - {8'h00, B};
            3'b011:  result_1c <= {8'h00, A} & {8'h00, B};
            3'b100:  result_1c <= {8'h00, A} ^ {8'h00, B};
            default: ;  // 3'b110 is free: it is the day 1 exercise
         endcase
      end
   end

   // done goes high on the edge if start is high and the op is not no_op
   always_ff @(posedge clk or negedge reset_n) begin
      if (!reset_n) done_1c <= 1'b0;
      else done_1c <= start && (op != 3'b000);
   end

endmodule : vtalu_1c

// Multi-cycle multiplication: done rises on the FOURTH clock edge after start
// (the one-cycle ops raise it on the first). The latency is deliberate: it is
// what forces the testbench to wait for 'done' instead of counting cycles.
module vtalu_mult (
    input  logic [ 7:0] A,
    input  logic [ 7:0] B,
    input  logic        clk,
    input  logic        reset_n,
    input  logic        start,
    output logic        done_mult,
    output logic [15:0] result_mult
);

   logic [7:0] a_int, b_int;  // input registers
   logic [15:0] mult1, mult2;  // pipeline registers
   logic done3, done2, done1;  // done travels down the same pipeline

   // Four register stages. done is pipelined alongside the data, and each
   // stage clears itself with (& ~done_mult): that is what makes done a
   // one-cycle pulse instead of staying high for as long as start does. It is
   // subtle -- it is copied straight from the VHDL.
   always_ff @(posedge clk or negedge reset_n) begin
      if (!reset_n) begin
         done_mult <= 1'b0;
         done3 <= 1'b0;
         done2 <= 1'b0;
         done1 <= 1'b0;
         a_int <= 8'h00;
         b_int <= 8'h00;
         mult1 <= 16'h0000;
         mult2 <= 16'h0000;
         result_mult <= 16'h0000;
      end else begin
         a_int <= A;
         b_int <= B;
         mult1 <= a_int * b_int;
         mult2 <= mult1;
         result_mult <= mult2;
         done3 <= start & ~done_mult;
         done2 <= done3 & ~done_mult;
         done1 <= done2 & ~done_mult;
         done_mult <= done1 & ~done_mult;
      end
   end

endmodule : vtalu_mult

// VTALU top: A, B, clk, op[2:0], reset_n, start -> done, ovf, result[15:0].
//
// The op is NOT decided by a single loose bit any more: there is a decode, which
// is what a real design does, and what lets the operations avoid having to sit
// in tidy halves of the opcode space.
//
//   no_op  3'b000      and_op 3'b011
//   add_op 3'b001      xor_op 3'b100
//   sub_op 3'b010      mul_op 3'b101
//                      3'b110 free -- the day 1 exercise
//   rst_op 3'b111 never reaches the DUT: the BFM turns it into lowering reset_n
module vtalu (
    input  logic [ 7:0] A,
    input  logic [ 7:0] B,
    input  logic        clk,
    input  logic [ 2:0] op,
    input  logic        reset_n,
    input  logic        start,
    output logic        done,
    output logic        ovf,
    output logic [15:0] result
);

   logic done_1c, done_mult;
   logic ovf_1c;
   logic [15:0] result_1c, result_mult, result_mux;
   logic start_1c, start_mult;
   logic es_mult;

   assign es_mult = (op == 3'b101);

   assign start_1c = es_mult ? 1'b0 : start;
   assign start_mult = es_mult ? start : 1'b0;
   assign result_mux = es_mult ? result_mult : result_1c;
   assign done = es_mult ? done_mult : done_1c;

   // The multiplication cannot overflow: 8 x 8 fits exactly in 16 bits.
   assign ovf = es_mult ? 1'b0 : ovf_1c;

   // The injectable mutation -- the only liberty taken in this DUT, and the same
   // one apb_regs.sv takes with its bug_en. With +VTALU_BUG, bit 0 of the result
   // comes out flipped for every operation. Nothing turns it on in a normal run:
   // it is 'make mutante' that runs the examples with it and DEMANDS that they
   // fail. A scoreboard that never caught anything is not tested, it is
   // decoration -- and until this existed there was no way of telling one from
   // the other.
   // It hangs off the decode above and not inside it so that the four lines the
   // day 1 slide quotes stay the plain mux they claim to be.
   bit bug;
   initial bug = $test$plusargs("VTALU_BUG");
   assign result = result_mux ^ {15'h0000, bug};

   vtalu_1c u_1c (
       .A        (A),
       .B        (B),
       .clk      (clk),
       .op       (op),
       .reset_n  (reset_n),
       .start    (start_1c),
       .done_1c  (done_1c),
       .ovf_1c   (ovf_1c),
       .result_1c(result_1c)
   );

   vtalu_mult u_mult (
       .A          (A),
       .B          (B),
       .clk        (clk),
       .reset_n    (reset_n),
       .start      (start_mult),
       .done_mult  (done_mult),
       .result_mult(result_mult)
   );

endmodule : vtalu

// Typical TB:
// ----------
//  * Functional Coverage
//  * Self Checking
//  * Constrained Random Stimulus

// Why is this bad?
//  * No modularity (everything in a single file)
//  * Almost nothing here can be reused
module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001,
                          sub_op = 3'b010,
                          and_op = 3'b011,
                          xor_op = 3'b100,
                          mul_op = 3'b101,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   wire         ovf;
   operation_t  op_set;

   assign op = op_set;

   vtalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .ovf, .result);

`ifdef VLT_TRACE
   // Waves for GTKWave:  VLT_TRACE=1 bash run.sh  &&  gtkwave vtalu.vcd
   // Behind an `ifdef because $dumpvars does not compile without --trace, and
   // the define comes from the same VLT_TRACE that adds the flag (common.sh).
   initial begin
      $dumpfile("vtalu.vcd");
      $dumpvars;
   end
`endif

   //op_cov: make sure every operation, and every interaction between them, is covered
   covergroup op_cov;
      coverpoint op_set {
         bins single_cycle[] = {[add_op : xor_op], rst_op,no_op};
         bins multi_cycle = {mul_op};

         // => are transitional coverage. From => To
         // Transition bins. Verilator 5.052 does NOT implement them yet: any form
         // with "=>" or "[* n]" aborts with an Internal Error. Minimal repro in
         // code/verilator/repro-cg-transition.sv. They stay because they are part
         // of the topic; when Verilator supports them, drop the ifndef, nothing else.
`ifndef VERILATOR
         bins opn_rst[] = ([add_op:mul_op] => rst_op);
         bins rst_opn[] = (rst_op => [add_op:mul_op]);

         bins sngl_mul[] = ([add_op:xor_op],no_op => mul_op);
         bins mul_sngl[] = (mul_op => [add_op:xor_op], no_op);

         bins twoops[] = ([add_op:mul_op] [* 2]);
         bins manymult = (mul_op [* 3:5]);
`endif
      }
   endgroup

   covergroup zeros_or_ones_on_ops;
      // Check the corners where the inputs are all 0s or all 1s
      all_ops : coverpoint op_set {
         ignore_bins null_ops = {rst_op, no_op};}

      a_leg: coverpoint A {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }

      b_leg: coverpoint B {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }
      // VTALU rev2: the borrow of the subtraction, the row of the plan that the
      // scoreboard can only close by looking at TWO outputs. Without this bin, a
      // subtraction that never went negative looks exactly like one that did.
      borrow: coverpoint ((op_set == sub_op) && (A < B)) {
         bins hubo_borrow = {1};
         ignore_bins resto = {0};
      }

      op_00_FF:  cross a_leg, b_leg, all_ops {
         bins add_00 = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins add_FF = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins sub_00 = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins sub_FF = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins and_00 = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins and_FF = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins xor_00 = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins xor_FF = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_00 = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins mul_FF = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_max = binsof (all_ops) intersect {mul_op} &&
                        (binsof (a_leg.ones) && binsof (b_leg.ones));

         ignore_bins others_only =
                         binsof(a_leg.others) && binsof(b_leg.others);
      }
   endgroup

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   op_cov oc;
   zeros_or_ones_on_ops c_00_FF;

   initial begin : coverage
      oc = new();
      c_00_FF = new();

      forever begin @(posedge clk);
         oc.sample();
         c_00_FF.sample();
      end
   end : coverage

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return sub_op;
        3'b011 : return and_op;
        3'b100 : return xor_op;
        3'b101 : return mul_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      // This is how the random gets biased
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   // Sent by the tester, compared by the scoreboard: the final block below
   // demands that the two match.
   int enviadas, chequeadas;

   // Scoreboard loop: checks that everything came out right
   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      bit      predicted_ovf;
      #1;
      case (op_set)
        add_op: predicted_result = A + B;
        sub_op: predicted_result = A - B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A ^ B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      // ovf belongs to sub and to nobody else: with 8-bit inputs and a 16-bit
      // output, neither the addition nor the multiplication can overflow.
      predicted_ovf = (op_set == sub_op) && (A < B);

      if ((op_set != no_op) && (op_set != rst_op)) begin
        chequeadas++;
        if (predicted_result != result || predicted_ovf != ovf)
          $error ("FAILED: A: %0h  B: %0h  op: %s result: %0h ovf: %0b",
                  A, B, op_set.name(), result, ovf);
      end
   end : scoreboard

   // Randomize the stimulus
   // get_op and get_data are Constrained Random Data
   // The point of CRD is to build values that are random but legal
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin
              // Wait for an EDGE with done up, not for done itself: on the
              // one-cycle ops done is a level still up from the previous op,
              // and a plain wait(done) drops this one without a sound.
              enviadas++;
              do @(negedge clk); while (done == 0);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      $finish;
   end : tester

   // The testbench checks itself: every operation sent has to come back
   // through the scoreboard. A tester that drops operations -- while the
   // coverage counts them anyway -- passes green and has measured nothing.
   final begin
      if (enviadas != chequeadas)
        $error ("sent %0d operations, the scoreboard checked %0d", enviadas, chequeadas);
      else
        $display ("%0d operations sent, %0d checked", enviadas, chequeadas);
   end
endmodule : top

// Typical TB:
// ----------
//  * Functional Coverage
//  * Self Checking
//  * Constrained Random Stimulus

// Why is this bad?
//  * No modularity (everything in a single file)
//  * Almost nothing here can be reused
module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001,
                          sub_op = 3'b010,
                          and_op = 3'b011,
                          xor_op = 3'b100,
                          mul_op = 3'b101,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   wire         ovf;
   operation_t  op_set;

   assign op = op_set;

   vtalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .ovf, .result);

`ifdef VLT_TRACE
   // Waves for GTKWave:  VLT_TRACE=1 bash run.sh  &&  gtkwave vtalu.vcd
   // Behind an `ifdef because $dumpvars does not compile without --trace, and
   // the define comes from the same VLT_TRACE that adds the flag (common.sh).
   initial begin
      $dumpfile("vtalu.vcd");
      $dumpvars;
   end
`endif

   //op_cov: make sure every operation, and every interaction between them, is covered
   covergroup op_cov;
      coverpoint op_set {
         bins single_cycle[] = {[add_op : xor_op], rst_op,no_op};
         bins multi_cycle = {mul_op};

         // => are transitional coverage. From => To
         // Transition bins. Verilator 5.052 does NOT implement them yet: any form
         // with "=>" or "[* n]" aborts with an Internal Error. Minimal repro in
         // code/verilator/repro-cg-transition.sv. They stay because they are part
         // of the topic; when Verilator supports them, drop the ifndef, nothing else.
`ifndef VERILATOR
         bins opn_rst[] = ([add_op:mul_op] => rst_op);
         bins rst_opn[] = (rst_op => [add_op:mul_op]);

         bins sngl_mul[] = ([add_op:xor_op],no_op => mul_op);
         bins mul_sngl[] = (mul_op => [add_op:xor_op], no_op);

         bins twoops[] = ([add_op:mul_op] [* 2]);
         bins manymult = (mul_op [* 3:5]);
`endif
      }
   endgroup

   covergroup zeros_or_ones_on_ops;
      // Check the corners where the inputs are all 0s or all 1s
      all_ops : coverpoint op_set {
         ignore_bins null_ops = {rst_op, no_op};}

      a_leg: coverpoint A {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }

      b_leg: coverpoint B {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }
      // VTALU rev2: the borrow of the subtraction, the row of the plan that the
      // scoreboard can only close by looking at TWO outputs. Without this bin, a
      // subtraction that never went negative looks exactly like one that did.
      borrow: coverpoint ((op_set == sub_op) && (A < B)) {
         bins hubo_borrow = {1};
         ignore_bins resto = {0};
      }

      op_00_FF:  cross a_leg, b_leg, all_ops {
         bins add_00 = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins add_FF = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins sub_00 = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins sub_FF = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins and_00 = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins and_FF = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins xor_00 = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins xor_FF = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_00 = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins mul_FF = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_max = binsof (all_ops) intersect {mul_op} &&
                        (binsof (a_leg.ones) && binsof (b_leg.ones));

         ignore_bins others_only =
                         binsof(a_leg.others) && binsof(b_leg.others);
      }
   endgroup

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   op_cov oc;
   zeros_or_ones_on_ops c_00_FF;

   initial begin : coverage
      oc = new();
      c_00_FF = new();

      forever begin @(posedge clk);
         oc.sample();
         c_00_FF.sample();
      end
   end : coverage

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return sub_op;
        3'b011 : return and_op;
        3'b100 : return xor_op;
        3'b101 : return mul_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      // This is how the random gets biased
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   // Sent by the tester, compared by the scoreboard: the final block below
   // demands that the two match.
   int enviadas, chequeadas;

   // Scoreboard loop: checks that everything came out right
   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      bit      predicted_ovf;
      #1;
      case (op_set)
        add_op: predicted_result = A + B;
        sub_op: predicted_result = A - B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A ^ B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      // ovf belongs to sub and to nobody else: with 8-bit inputs and a 16-bit
      // output, neither the addition nor the multiplication can overflow.
      predicted_ovf = (op_set == sub_op) && (A < B);

      if ((op_set != no_op) && (op_set != rst_op)) begin
        chequeadas++;
        if (predicted_result != result || predicted_ovf != ovf)
          $error ("FAILED: A: %0h  B: %0h  op: %s result: %0h ovf: %0b",
                  A, B, op_set.name(), result, ovf);
      end
   end : scoreboard

   // Randomize the stimulus
   // get_op and get_data are Constrained Random Data
   // The point of CRD is to build values that are random but legal
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin
              // Wait for an EDGE with done up, not for done itself: on the
              // one-cycle ops done is a level still up from the previous op,
              // and a plain wait(done) drops this one without a sound.
              enviadas++;
              do @(negedge clk); while (done == 0);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      $finish;
   end : tester

   // The testbench checks itself: every operation sent has to come back
   // through the scoreboard. A tester that drops operations -- while the
   // coverage counts them anyway -- passes green and has measured nothing.
   final begin
      if (enviadas != chequeadas)
        $error ("sent %0d operations, the scoreboard checked %0d", enviadas, chequeadas);
      else
        $display ("%0d operations sent, %0d checked", enviadas, chequeadas);
   end
endmodule : top

// Typical TB:
// ----------
//  * Functional Coverage
//  * Self Checking
//  * Constrained Random Stimulus

// Why is this bad?
//  * No modularity (everything in a single file)
//  * Almost nothing here can be reused
module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001,
                          sub_op = 3'b010,
                          and_op = 3'b011,
                          xor_op = 3'b100,
                          mul_op = 3'b101,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   wire         ovf;
   operation_t  op_set;

   assign op = op_set;

   vtalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .ovf, .result);

`ifdef VLT_TRACE
   // Waves for GTKWave:  VLT_TRACE=1 bash run.sh  &&  gtkwave vtalu.vcd
   // Behind an `ifdef because $dumpvars does not compile without --trace, and
   // the define comes from the same VLT_TRACE that adds the flag (common.sh).
   initial begin
      $dumpfile("vtalu.vcd");
      $dumpvars;
   end
`endif

   //op_cov: make sure every operation, and every interaction between them, is covered
   covergroup op_cov;
      coverpoint op_set {
         bins single_cycle[] = {[add_op : xor_op], rst_op,no_op};
         bins multi_cycle = {mul_op};

         // => are transitional coverage. From => To
         // Transition bins. Verilator 5.052 does NOT implement them yet: any form
         // with "=>" or "[* n]" aborts with an Internal Error. Minimal repro in
         // code/verilator/repro-cg-transition.sv. They stay because they are part
         // of the topic; when Verilator supports them, drop the ifndef, nothing else.
`ifndef VERILATOR
         bins opn_rst[] = ([add_op:mul_op] => rst_op);
         bins rst_opn[] = (rst_op => [add_op:mul_op]);

         bins sngl_mul[] = ([add_op:xor_op],no_op => mul_op);
         bins mul_sngl[] = (mul_op => [add_op:xor_op], no_op);

         bins twoops[] = ([add_op:mul_op] [* 2]);
         bins manymult = (mul_op [* 3:5]);
`endif
      }
   endgroup

   covergroup zeros_or_ones_on_ops;
      // Check the corners where the inputs are all 0s or all 1s
      all_ops : coverpoint op_set {
         ignore_bins null_ops = {rst_op, no_op};}

      a_leg: coverpoint A {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }

      b_leg: coverpoint B {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }
      // VTALU rev2: the borrow of the subtraction, the row of the plan that the
      // scoreboard can only close by looking at TWO outputs. Without this bin, a
      // subtraction that never went negative looks exactly like one that did.
      borrow: coverpoint ((op_set == sub_op) && (A < B)) {
         bins hubo_borrow = {1};
         ignore_bins resto = {0};
      }

      op_00_FF:  cross a_leg, b_leg, all_ops {
         bins add_00 = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins add_FF = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins sub_00 = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins sub_FF = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins and_00 = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins and_FF = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins xor_00 = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins xor_FF = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_00 = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins mul_FF = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_max = binsof (all_ops) intersect {mul_op} &&
                        (binsof (a_leg.ones) && binsof (b_leg.ones));

         ignore_bins others_only =
                         binsof(a_leg.others) && binsof(b_leg.others);
      }
   endgroup

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   op_cov oc;
   zeros_or_ones_on_ops c_00_FF;

   initial begin : coverage
      oc = new();
      c_00_FF = new();

      forever begin @(posedge clk);
         oc.sample();
         c_00_FF.sample();
      end
   end : coverage

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return sub_op;
        3'b011 : return and_op;
        3'b100 : return xor_op;
        3'b101 : return mul_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      // This is how the random gets biased
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   // Sent by the tester, compared by the scoreboard: the final block below
   // demands that the two match.
   int enviadas, chequeadas;

   // Scoreboard loop: checks that everything came out right
   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      bit      predicted_ovf;
      #1;
      case (op_set)
        add_op: predicted_result = A + B;
        sub_op: predicted_result = A - B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A ^ B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      // ovf belongs to sub and to nobody else: with 8-bit inputs and a 16-bit
      // output, neither the addition nor the multiplication can overflow.
      predicted_ovf = (op_set == sub_op) && (A < B);

      if ((op_set != no_op) && (op_set != rst_op)) begin
        chequeadas++;
        if (predicted_result != result || predicted_ovf != ovf)
          $error ("FAILED: A: %0h  B: %0h  op: %s result: %0h ovf: %0b",
                  A, B, op_set.name(), result, ovf);
      end
   end : scoreboard

   // Randomize the stimulus
   // get_op and get_data are Constrained Random Data
   // The point of CRD is to build values that are random but legal
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin
              // Wait for an EDGE with done up, not for done itself: on the
              // one-cycle ops done is a level still up from the previous op,
              // and a plain wait(done) drops this one without a sound.
              enviadas++;
              do @(negedge clk); while (done == 0);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      $finish;
   end : tester

   // The testbench checks itself: every operation sent has to come back
   // through the scoreboard. A tester that drops operations -- while the
   // coverage counts them anyway -- passes green and has measured nothing.
   final begin
      if (enviadas != chequeadas)
        $error ("sent %0d operations, the scoreboard checked %0d", enviadas, chequeadas);
      else
        $display ("%0d operations sent, %0d checked", enviadas, chequeadas);
   end
endmodule : top

// Typical TB:
// ----------
//  * Functional Coverage
//  * Self Checking
//  * Constrained Random Stimulus

// Why is this bad?
//  * No modularity (everything in a single file)
//  * Almost nothing here can be reused
module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001,
                          sub_op = 3'b010,
                          and_op = 3'b011,
                          xor_op = 3'b100,
                          mul_op = 3'b101,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   wire         ovf;
   operation_t  op_set;

   assign op = op_set;

   vtalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .ovf, .result);

`ifdef VLT_TRACE
   // Waves for GTKWave:  VLT_TRACE=1 bash run.sh  &&  gtkwave vtalu.vcd
   // Behind an `ifdef because $dumpvars does not compile without --trace, and
   // the define comes from the same VLT_TRACE that adds the flag (common.sh).
   initial begin
      $dumpfile("vtalu.vcd");
      $dumpvars;
   end
`endif

   //op_cov: make sure every operation, and every interaction between them, is covered
   covergroup op_cov;
      coverpoint op_set {
         bins single_cycle[] = {[add_op : xor_op], rst_op,no_op};
         bins multi_cycle = {mul_op};

         // => are transitional coverage. From => To
         // Transition bins. Verilator 5.052 does NOT implement them yet: any form
         // with "=>" or "[* n]" aborts with an Internal Error. Minimal repro in
         // code/verilator/repro-cg-transition.sv. They stay because they are part
         // of the topic; when Verilator supports them, drop the ifndef, nothing else.
`ifndef VERILATOR
         bins opn_rst[] = ([add_op:mul_op] => rst_op);
         bins rst_opn[] = (rst_op => [add_op:mul_op]);

         bins sngl_mul[] = ([add_op:xor_op],no_op => mul_op);
         bins mul_sngl[] = (mul_op => [add_op:xor_op], no_op);

         bins twoops[] = ([add_op:mul_op] [* 2]);
         bins manymult = (mul_op [* 3:5]);
`endif
      }
   endgroup

   covergroup zeros_or_ones_on_ops;
      // Check the corners where the inputs are all 0s or all 1s
      all_ops : coverpoint op_set {
         ignore_bins null_ops = {rst_op, no_op};}

      a_leg: coverpoint A {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }

      b_leg: coverpoint B {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }
      // VTALU rev2: the borrow of the subtraction, the row of the plan that the
      // scoreboard can only close by looking at TWO outputs. Without this bin, a
      // subtraction that never went negative looks exactly like one that did.
      borrow: coverpoint ((op_set == sub_op) && (A < B)) {
         bins hubo_borrow = {1};
         ignore_bins resto = {0};
      }

      op_00_FF:  cross a_leg, b_leg, all_ops {
         bins add_00 = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins add_FF = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins sub_00 = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins sub_FF = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins and_00 = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins and_FF = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins xor_00 = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins xor_FF = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_00 = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins mul_FF = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_max = binsof (all_ops) intersect {mul_op} &&
                        (binsof (a_leg.ones) && binsof (b_leg.ones));

         ignore_bins others_only =
                         binsof(a_leg.others) && binsof(b_leg.others);
      }
   endgroup

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   op_cov oc;
   zeros_or_ones_on_ops c_00_FF;

   initial begin : coverage
      oc = new();
      c_00_FF = new();

      forever begin @(posedge clk);
         oc.sample();
         c_00_FF.sample();
      end
   end : coverage

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return sub_op;
        3'b011 : return and_op;
        3'b100 : return xor_op;
        3'b101 : return mul_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      // This is how the random gets biased
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   // Sent by the tester, compared by the scoreboard: the final block below
   // demands that the two match.
   int enviadas, chequeadas;

   // Scoreboard loop: checks that everything came out right
   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      bit      predicted_ovf;
      #1;
      case (op_set)
        add_op: predicted_result = A + B;
        sub_op: predicted_result = A - B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A ^ B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      // ovf belongs to sub and to nobody else: with 8-bit inputs and a 16-bit
      // output, neither the addition nor the multiplication can overflow.
      predicted_ovf = (op_set == sub_op) && (A < B);

      if ((op_set != no_op) && (op_set != rst_op)) begin
        chequeadas++;
        if (predicted_result != result || predicted_ovf != ovf)
          $error ("FAILED: A: %0h  B: %0h  op: %s result: %0h ovf: %0b",
                  A, B, op_set.name(), result, ovf);
      end
   end : scoreboard

   // Randomize the stimulus
   // get_op and get_data are Constrained Random Data
   // The point of CRD is to build values that are random but legal
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin
              // Wait for an EDGE with done up, not for done itself: on the
              // one-cycle ops done is a level still up from the previous op,
              // and a plain wait(done) drops this one without a sound.
              enviadas++;
              do @(negedge clk); while (done == 0);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      $finish;
   end : tester

   // The testbench checks itself: every operation sent has to come back
   // through the scoreboard. A tester that drops operations -- while the
   // coverage counts them anyway -- passes green and has measured nothing.
   final begin
      if (enviadas != chequeadas)
        $error ("sent %0d operations, the scoreboard checked %0d", enviadas, chequeadas);
      else
        $display ("%0d operations sent, %0d checked", enviadas, chequeadas);
   end
endmodule : top

// Typical TB:
// ----------
//  * Functional Coverage
//  * Self Checking
//  * Constrained Random Stimulus

// Why is this bad?
//  * No modularity (everything in a single file)
//  * Almost nothing here can be reused
module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001,
                          sub_op = 3'b010,
                          and_op = 3'b011,
                          xor_op = 3'b100,
                          mul_op = 3'b101,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   wire         ovf;
   operation_t  op_set;

   assign op = op_set;

   vtalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .ovf, .result);

`ifdef VLT_TRACE
   // Waves for GTKWave:  VLT_TRACE=1 bash run.sh  &&  gtkwave vtalu.vcd
   // Behind an `ifdef because $dumpvars does not compile without --trace, and
   // the define comes from the same VLT_TRACE that adds the flag (common.sh).
   initial begin
      $dumpfile("vtalu.vcd");
      $dumpvars;
   end
`endif

   //op_cov: make sure every operation, and every interaction between them, is covered
   covergroup op_cov;
      coverpoint op_set {
         bins single_cycle[] = {[add_op : xor_op], rst_op,no_op};
         bins multi_cycle = {mul_op};

         // => are transitional coverage. From => To
         // Transition bins. Verilator 5.052 does NOT implement them yet: any form
         // with "=>" or "[* n]" aborts with an Internal Error. Minimal repro in
         // code/verilator/repro-cg-transition.sv. They stay because they are part
         // of the topic; when Verilator supports them, drop the ifndef, nothing else.
`ifndef VERILATOR
         bins opn_rst[] = ([add_op:mul_op] => rst_op);
         bins rst_opn[] = (rst_op => [add_op:mul_op]);

         bins sngl_mul[] = ([add_op:xor_op],no_op => mul_op);
         bins mul_sngl[] = (mul_op => [add_op:xor_op], no_op);

         bins twoops[] = ([add_op:mul_op] [* 2]);
         bins manymult = (mul_op [* 3:5]);
`endif
      }
   endgroup

   covergroup zeros_or_ones_on_ops;
      // Check the corners where the inputs are all 0s or all 1s
      all_ops : coverpoint op_set {
         ignore_bins null_ops = {rst_op, no_op};}

      a_leg: coverpoint A {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }

      b_leg: coverpoint B {
         bins zeros = {8'h00};
         bins others= {[8'h01:8'hFE]};
         bins ones  = {8'hFF};
      }
      // VTALU rev2: the borrow of the subtraction, the row of the plan that the
      // scoreboard can only close by looking at TWO outputs. Without this bin, a
      // subtraction that never went negative looks exactly like one that did.
      borrow: coverpoint ((op_set == sub_op) && (A < B)) {
         bins hubo_borrow = {1};
         ignore_bins resto = {0};
      }

      op_00_FF:  cross a_leg, b_leg, all_ops {
         bins add_00 = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins add_FF = binsof (all_ops) intersect {add_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins sub_00 = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins sub_FF = binsof (all_ops) intersect {sub_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins and_00 = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins and_FF = binsof (all_ops) intersect {and_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins xor_00 = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins xor_FF = binsof (all_ops) intersect {xor_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_00 = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.zeros) || binsof (b_leg.zeros));

         bins mul_FF = binsof (all_ops) intersect {mul_op} &&
                       (binsof (a_leg.ones) || binsof (b_leg.ones));

         bins mul_max = binsof (all_ops) intersect {mul_op} &&
                        (binsof (a_leg.ones) && binsof (b_leg.ones));

         ignore_bins others_only =
                         binsof(a_leg.others) && binsof(b_leg.others);
      }
   endgroup

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   op_cov oc;
   zeros_or_ones_on_ops c_00_FF;

   initial begin : coverage
      oc = new();
      c_00_FF = new();

      forever begin @(posedge clk);
         oc.sample();
         c_00_FF.sample();
      end
   end : coverage

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return sub_op;
        3'b011 : return and_op;
        3'b100 : return xor_op;
        3'b101 : return mul_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      // This is how the random gets biased
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   // Sent by the tester, compared by the scoreboard: the final block below
   // demands that the two match.
   int enviadas, chequeadas;

   // Scoreboard loop: checks that everything came out right
   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      bit      predicted_ovf;
      #1;
      case (op_set)
        add_op: predicted_result = A + B;
        sub_op: predicted_result = A - B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A ^ B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      // ovf belongs to sub and to nobody else: with 8-bit inputs and a 16-bit
      // output, neither the addition nor the multiplication can overflow.
      predicted_ovf = (op_set == sub_op) && (A < B);

      if ((op_set != no_op) && (op_set != rst_op)) begin
        chequeadas++;
        if (predicted_result != result || predicted_ovf != ovf)
          $error ("FAILED: A: %0h  B: %0h  op: %s result: %0h ovf: %0b",
                  A, B, op_set.name(), result, ovf);
      end
   end : scoreboard

   // Randomize the stimulus
   // get_op and get_data are Constrained Random Data
   // The point of CRD is to build values that are random but legal
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin
              // Wait for an EDGE with done up, not for done itself: on the
              // one-cycle ops done is a level still up from the previous op,
              // and a plain wait(done) drops this one without a sound.
              enviadas++;
              do @(negedge clk); while (done == 0);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      $finish;
   end : tester

   // The testbench checks itself: every operation sent has to come back
   // through the scoreboard. A tester that drops operations -- while the
   // coverage counts them anyway -- passes green and has measured nothing.
   final begin
      if (enviadas != chequeadas)
        $error ("sent %0d operations, the scoreboard checked %0d", enviadas, chequeadas);
      else
        $display ("%0d operations sent, %0d checked", enviadas, chequeadas);
   end
endmodule : top

interface vtalu_bfm;
   // brings in operation_t. e.g. (no_op  = 3'b000)
   import vtalu_pkg::*;

   byte unsigned        A;
   byte unsigned        B;
   bit                  clk;
   bit                  reset_n;
   wire          [ 2:0] op;
   bit                  start;
   wire                 done;
   wire          [15:0] result;
   wire                 ovf;
   operation_t          op_set;

   assign op = op_set;

   // The BFM is a first step towards modularity
   // It takes care of driving every low-level signal
   // and keeps the protocol in one single place

   // DUT clock
   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   // DUT reset
   task reset_alu();
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
   endtask : reset_alu

   // The protocol handling can now be changed in one single place.
   // Fix it here once, and the fix propagates through the rest of the code
   task send_op(input byte iA, input byte iB, input operation_t iop,
                output shortint alu_result);

      op_set = iop;

      if (iop == rst_op) begin
         @(posedge clk);
         reset_n = 1'b0;
         start = 1'b0;
         @(posedge clk);
         #1;
         reset_n = 1'b1;
      end else begin
         @(negedge clk);
         A = iA;
         B = iB;
         start = 1'b1;
         if (iop == no_op) begin
            @(posedge clk);
            #1;
            start = 1'b0;
         end else begin
            do @(negedge clk); while (done == 0);
            start = 1'b0;
         end
      end

   endtask : send_op

endinterface : vtalu_bfm

interface vtalu_bfm;
   // brings in operation_t. e.g. (no_op  = 3'b000)
   import vtalu_pkg::*;

   byte unsigned        A;
   byte unsigned        B;
   bit                  clk;
   bit                  reset_n;
   wire          [ 2:0] op;
   bit                  start;
   wire                 done;
   wire          [15:0] result;
   wire                 ovf;
   operation_t          op_set;

   assign op = op_set;

   // The BFM is a first step towards modularity
   // It takes care of driving every low-level signal
   // and keeps the protocol in one single place

   // DUT clock
   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end

   // DUT reset
   task reset_alu();
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
   endtask : reset_alu

   // The protocol handling can now be changed in one single place.
   // Fix it here once, and the fix propagates through the rest of the code
   task send_op(input byte iA, input byte iB, input operation_t iop,
                output shortint alu_result);

      op_set = iop;

      if (iop == rst_op) begin
         @(posedge clk);
         reset_n = 1'b0;
         start = 1'b0;
         @(posedge clk);
         #1;
         reset_n = 1'b1;
      end else begin
         @(negedge clk);
         A = iA;
         B = iB;
         start = 1'b1;
         if (iop == no_op) begin
            @(posedge clk);
            #1;
            start = 1'b0;
         end else begin
            do @(negedge clk); while (done == 0);
            start = 1'b0;
         end
      end

   endtask : send_op

endinterface : vtalu_bfm

// The Tester module is simpler now, because it no
// longer has to deal with low-level signals
module tester (
    vtalu_bfm bfm
);
   import vtalu_pkg::*;

   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
         3'b000: return no_op;
         3'b001: return add_op;
         3'b010: return sub_op;
         3'b011: return and_op;
         3'b100: return xor_op;
         3'b101: return mul_op;
         3'b110: return rst_op;
         3'b111: return rst_op;
      endcase  // case (op_choice)
   endfunction : get_op

   function byte get_data();
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00) return 8'h00;
      else if (zero_ones == 2'b11) return 8'hFF;
      else return $random;
   endfunction : get_data

   initial begin
      byte unsigned iA;
      byte unsigned iB;
      operation_t   op_set;
      shortint      result;

      bfm.reset_alu();
      repeat (1000) begin : random_loop
         op_set = get_op();
         iA = get_data();
         iB = get_data();
         bfm.send_op(iA, iB, op_set, result);
      end : random_loop
      $finish;
   end  // initial begin
endmodule : tester

// Sampling by hand: without a clocking block you have to pick the edge AND the
// delta, in every task, over and over. This top runs the three variants people
// write in their first week: one reads the OLD value, the other two the NEW.
//
//   bash run.sh
module dut_reg (input bit clk, input byte unsigned d_in, output byte unsigned d_out);
   // The DUT counts: on every edge, the output becomes the input + 1.
   always_ff @(posedge clk) d_out <= d_in + 8'd1;
endmodule

module top_sin;
   bit           clk = 0;
   byte unsigned d_in, d_out;

   always #5 clk = ~clk;
   dut_reg u_dut (.*);

   byte unsigned en_el_flanco, un_delta_despues, en_el_flanco_opuesto;

   initial begin
      d_in = 8'd10;

      // 1. Sample AT the edge. The DUT always_ff updates d_out with a
      //    nonblocking assignment, which lands after this initial already ran:
      //    you read the OLD value.
      @(posedge clk);
      en_el_flanco = d_out;

      // 2. The same edge, one delta later. The nonblocking assignment landed
      //    already and you read the NEW value. That "#1" is visible nowhere and
      //    changes the result.
      @(posedge clk);
      #1;
      un_delta_despues = d_out;

      // 3. The opposite edge: the trick the whole course BFM uses. It works,
      //    but it asks whoever reads it to know why.
      @(negedge clk);
      en_el_flanco_opuesto = d_out;

      $display("d_in = %0d, and the DUT computes d_in + 1 = %0d", 8'd10, 8'd11);
      $display("  sampled AT the posedge        : %0d", en_el_flanco);
      $display("  sampled one delta later       : %0d", un_delta_despues);
      $display("  sampled at the negedge        : %0d", en_el_flanco_opuesto);
      $display("");
      $display("Three lines that look the same and are not. And that decision");
      $display("is repeated in every task of the interface.");
      $finish;
   end
endmodule : top_sin

// The same DUT, with a clocking block: the edge and the delta are declared ONCE,
// inside the interface, and no task ever picks them again.
//
//   bash run.sh
module dut_reg (input bit clk, input byte unsigned d_in, output byte unsigned d_out);
   always_ff @(posedge clk) d_out <= d_in + 8'd1;
endmodule

interface reg_bfm (input bit clk);
   byte unsigned d_in, d_out;

   // The only two timing lines in the testbench:
   //   input  #1step  samples the STABLE value right before the edge, which is
   //                  what the hardware sees. Never what the nonblocking
   //                  assignment just wrote on that same edge.
   //   output #0      drives ON the edge, in the nonblocking region, so the DUT
   //                  does not see it until the next edge.
   clocking cb @(posedge clk);
      default input #1step output #0;
      output d_in;
      input  d_out;
   endclocking

   modport tb (clocking cb);
endinterface : reg_bfm

module top_con;
   bit clk = 0;
   always #5 clk = ~clk;

   reg_bfm bfm (clk);
   dut_reg u_dut (.clk(clk), .d_in(bfm.d_in), .d_out(bfm.d_out));

   byte unsigned primera, segunda, tercera;

   initial begin
      // Driving is "<=" against the clocking block. There is no edge to pick.
      bfm.cb.d_in <= 8'd10;

      // @(bfm.cb) is "wait for this clocking block's edge". There are THREE, and
      // the reason is the whole lesson:
      //   1st edge  the output #0 only now puts d_in at 10, in the nonblocking
      //             region, so the DUT has not seen it yet.
      //   2nd edge  now the DUT takes d_in=10 and computes d_out <= 11.
      //   3rd edge  the input #1step samples the STABLE value before this edge,
      //             which is already 11.
      // A testbench without a clocking block hides this behind a #1 and works by
      // accident. Here the arithmetic is visible and does not depend on the tool.
      @(bfm.cb);
      @(bfm.cb);
      @(bfm.cb);

      // And sampling is reading cb.d_out. It is read three times, at three
      // different points of the same cycle, and gives the same value all three.
      primera = bfm.cb.d_out;
      #2;
      segunda = bfm.cb.d_out;
      #3;
      tercera = bfm.cb.d_out;

      $display("d_in = %0d, and the DUT computes d_in + 1 = %0d", 8'd10, 8'd11);
      $display("  cb.d_out, right after the edge  : %0d", primera);
      $display("  cb.d_out, two units later       : %0d", segunda);
      $display("  cb.d_out, five later            : %0d", tercera);
      $display("");
      $display("The same number all three times, and not a single #1 in the testbench.");
      $display("The edge and the delta were declared once, in the clocking block.");

      if (primera != 8'd11 || segunda != 8'd11 || tercera != 8'd11)
        $fatal(1, "the clocking block should give 11 all three times");
      $finish;
   end
endmodule : top_con

// The trap that comes with the clocking block: mixing the two domains.
//
// Once a signal belongs to a clocking block, there are TWO names for the same
// wire -- bfm.d_out and bfm.cb.d_out -- and they are NOT the same value. One is
// the live wire; the other is what the clocking block sampled #1step before the
// edge. On a signal that changes every cycle they differ by exactly one cycle.
//
// Nothing warns about this: it compiles, it runs, and a scoreboard that reads
// one of them while the monitor reads the other fails intermittently.
//
//   bash run.sh
module contador (input bit clk, output byte unsigned d_out);
   // Counts on every edge, so the live wire and the sampled one never agree.
   always_ff @(posedge clk) d_out <= d_out + 8'd1;
endmodule

interface cnt_bfm (input bit clk);
   byte unsigned d_out;
   clocking cb @(posedge clk);
      default input #1step;
      input d_out;
   endclocking
endinterface : cnt_bfm

module top_mezcla;
   bit clk = 0;
   always #5 clk = ~clk;

   cnt_bfm bfm (clk);
   contador u_cnt (.clk(clk), .d_out(bfm.d_out));

   byte unsigned por_cb, crudo;

   initial begin
      repeat (4) @(bfm.cb);

      // The two reads, at the SAME instant, on the SAME wire.
      por_cb = bfm.cb.d_out;
      crudo  = bfm.d_out;

      $display("at the same instant, on the same wire:");
      $display("  bfm.cb.d_out (what the clocking block sampled) : %0d", por_cb);
      $display("  bfm.d_out    (the live wire)                   : %0d", crudo);
      $display("");
      $display("They differ by one cycle, and no warning says so. A monitor that");
      $display("reads through the clocking block and a scoreboard that reads the");
      $display("raw wire do not fail every time: they fail when the data changes.");

      if (por_cb == crudo)
        $fatal(1, "they were expected to differ: the example stopped showing the trap");
      $finish;
   end
endmodule : top_mezcla